Conventional planar MOSFET devices have been scaling down over the last few decades to provide higher integration density, higher operation speed and lower cost. However, the scaling down of MOSFET devices is restricted by the short channel effect which causes a high leakage current. In order to counteract the short channel effect, FinFETs have started being used due to the FinFETs stronger gate electrostatic control over the channel which can mitigate the short channel effect. However, the fabrication of FinFETs is more challenging than conventional planar device fabrication because of the high topology of the fins.
During conventional FinFET fabrication, the fin is formed first. Then the gate, spacer and junction/contact may be formed. As the gate, spacer and junction are formed they must be formed over and around the high topology fins. The high topology fins may cause challenges during deposition, lithography and etching to form the gate, spacer, and junction. Further, epitaxy must be grown on the three dimensional fin rather than the previous two dimensional planar substrate, this results in less epitaxy volume on the three dimensional fin than was previously on the planar substrate thereby limiting the stress enhancement. With a limited epitaxy volume on the three dimensional fins, the silicidation cannot consume too much epitaxy material. Currently, titanium silicide is being used because it consumes less epitaxy, however titanium silicide has poor contact properties.
Thus, the fabrication of FinFET devices can be problematic with existing fabrication techniques and improved FinFET fabrication techniques are needed for forming FinFET devices to improve the performance of the resultant semiconductors.